CPRE 587 is Hardware Design for Machine learning at Iowa State. It gives a background on machine learning and explores various ways to Accelerate it with hardware designs. I choose to take it Fall 2024 to grow in my understanding of machine learning and to improve my digital design capabilities.

My lab partner and I came up with the final project of designing a MAC accelerator for fabrication with the new club of Chip forge at Iowa State. The club does ASIC design and orders a chip for fabrication each semester. We build a MAC unit that could do 32-bit, 2 16-bit, 4 8-bit, 8 4-bit, or 16 2-bit MACs. This MAC unit is coupled with a very minimalist RISC-V processor which the Chipforge club builds around due to using the eFabless tool set. We saw significant speed up with our design as it did not increase critical path but did give multiplication capabilities which otherwise had to be handled in software. The chip is set to come back Spring 2025. After we designed it and verified it in simulation we put the design on the FPGA for further testing and profiling speedup. More details are in our report below.

With extra time at the end of the semester to give our accelerator a meaningful workload. I trained a deep neural network for Iris identification from the Iris dataset achieving a 96% accuracy. The main challenge on this was getting it to fit on the tiny memory that the processor has. Additionally it built up my experience with fixed point math as I worked to get it to run on our design flashed on a FPGA. More details are in the design document.